The present invention relates to an image sensing apparatus using a solid-state image sensing element such as a charge coupled device (CCD) and, more particularly, to an image sensing apparatus wherein a camera head unit and a video processor unit are separately arranged and are connected through a cable, a solid-state image sensing element and its peripheral circuit are arranged in the camera head unit, and a driver for the solid-state 10 image sensing element and a signal processor for processing an image signal output from the solid-state image sensing element to convert it into a video signal, are arranged in the video processor unit.
FIG. 1 is a plan view of solid-state image sensing element 10 using an interline transfer type CCD. A light-receiving portion of element 10 consists of photodiodes 16 arranged in a matrix. Charges generated from each array (vertical array) of photodiodes 16 are supplied to vertical transfer CCD 12 through read gate 18. Read gate 18 is connected to read gate terminal LG. A +3 V power supply voltage (DC voltage) is applied to terminal LG.
Vertical transfer CCD 12 is driven by a 4-phase clock signal consisting of vertical drive pulses .phi.V1l, .phi.V2, .phi.V3, and .phi.V4, and charges generated from photodiodes 16 are read out and transferred at a predetermined timing. The charges transferred through CCD 12 are supplied to horizontal transfer CCD 14 for each horizontal scanning line.
CCD 14 transfers the charges supplied from CCD 12 for each scanning line. CCD 14 is driven in response to a 4-phase clock signal consisting of horizontal drive pulses .phi.H1, .phi.H2, .phi.H3, and .phi.H4.
Output gate 20 is connected to the output terminal of CCD 14, and receives a +7 V power supply voltage through output gate terminal OG. The signal charges 10 output through output gate 20 are supplied to the gate of output transistor 22 comprising a field effect transistor (FET). An image signal corresponding to the signal charges from photodiodes 16 can be output through the source of transistor 22 and signal output terminal Vout. A +16 V drain voltage is applied to the drain of output transistor 22 through output drain terminal OD.
The gate of transistor 22 is connected to the source of reset transistor 24 comprising an FET. After the image signals are output from photodiodes 16, the charges applied to the gate of transistor 22 are discharged from reset drain terminal RD through the drain of reset transistor 24 at a predetermined timing defined by reset pulses .phi.R. A +16 V power supply voltage is also applied to reset drain terminal RD.
A 0 V power supply voltage is applied to P-well terminal PW of element 10, and a +8 V power supply voltage is applied to substrate bias terminal SUB.
In this manner, solid-state image sensing element 10 requires four types of power supply voltages, i.e., +16 V, +8 V, +7 V, and +3 V. When element 10 is arranged in the camera head unit, the four power supply voltages are obtained by voltage-dividing a single +16 V power supply voltage supplied from video processor unit 42, as shown in FIG. 2.
Camera head unit 40 incorporating element 10 is connected to video processor unit 42 having a power supply circuit, a video signal processor, and the like, through cable 38. Signal output terminal Vout of element 10 is connected to the base of output buffer transistor Q1, and the image signal is amplified and output from the emitter. The emitter output from transistor Q1 is transmitted to a video signal processor (not shown) in video processor unit 42 through an internal conductor of coaxial cable 46. The video signal processed by unit 42 is supplied to and is displayed on CRT monitor 44.
The outer conductor of coaxial cable 46 is grounded inside the unit 42.
A +16 V power supply voltage is applied to the collector of transistor Q1 from unit 42 through cable 38. Voltage dividing resistors R1, R2, R3, and R4 are connected in series with each other between the collector of transistor Q1 and the outer conductor (ground potential) of coaxial cable 46. The ratio of resistances of resistors R1, R2, R3, and R4 is set so that voltages at voltage dividing points are respectively +8 V, +7 V, and +3 V.
A +16 V voltage terminal (the collector of transistor Q1) is connected to reset drain terminal RD and output drain terminal OD of element 10. A +8 V voltage terminal (the node between resistors R1 and R2) is connected to substrate bias terminal SUB of element 10. A +7 V voltage terminal (the node between resistors R2 and R3) is connected to output gate terminal OG of element 10. A +3 V voltage terminal (the node between resistors R3 and R4) is connected to read gate terminal LG of element 10. A ground terminal (the outer conductor of coaxial cable 46) is connected to P-well terminal PW of element 10.
The +16 V, +8 V, +7 V, and +3 V voltage terminals are grounded (connected to the outer conductor of cable 46) through bypass capacitors C1, C2, C3, and C4, respectively. These capacitors C1, C2, C3, and C4 are impedance conversion elements for decreasing AC impedances of the voltage terminals of element 10, and must be arranged as near as possible to element 10.
According to the prior art apparatus, transistor Q1, resistors R1, R2, R3, and R4, and capacitors C1, C2, C3, and C4 are arranged near element 10. For this reason, even if these components are arranged using chip parts, a total of 9 parts are necessary. Therefore, even if these components are arranged on a single printed circuit board, they interfere with the reduction in size of camera head unit 40. This particularly poses a problem in an electronic endoscope which incorporates an image sensing element at its distal end portion.
If the video processor unit and the camera head unit are separately arranged, the following problems are also posed. Unit 42 supplies various drive pulses (clock pulses) to unit 40, and samples and holds discrete image signals for each pixel output from element 10 at a timing corresponding to the drive pulse to obtain an analogue continuous image signal. Cable 38 connecting units 42 and 40 delays a signal transmission time. Cables 38 having various lengths are prepared. Therefore, if the sample and hold timing is fixed, the timing of the clock pulses may be offset from the sample and hold timing in accordance with the length of cable 38.
In order to solve this problem, it can be considered that a plurality of delay circuits for delaying the drive pulses by various delay times corresponding to the various lengths of cables 38 and a selector for selecting one output from the delay circuits in accordance with the length of cable 38 and supplying the selected output to unit 40 are arranged in unit 42. However, with this method, the circuit arrangement of unit 42 is complicated and becomes bulky if a large number of cables 38 having different lengths are prepared. When the image sensing apparatus is applied to endoscopes, since endoscopes have cables of various lengths, this poses a serious problem.